Semiconductor devices are packaged using a metal, plastic or ceramic package to protect the semiconductor device from impact, corrosion and moisture. Packages also provide a connection means between the semiconductor device inside the package and circuitry outside the package. The package may also dissipate heat generated in the semiconductor device during operation.
Packages include metal connections that electrically connect the semiconductor device to the external world. These connections, known as leads, may be soldered to circuit boards or other external components. Packages that are molded around the semiconductor device, for example plastic packages, additionally provide a mechanical means to hold the leads in place.
If dissipation of heat and sealing of the semiconductor device within the package are critical to the operation of the semiconductor device, a ceramic package may be desired. Packaging materials in the ceramic package provide good thermal conductivity and hermeticity.
Electrical parasitics, or for example inductance and resistance, can degrade the electrical characteristics of the packaged device. Electrical parasitics are an unavoidable and unwanted electrical character that exists between the parts of an electronic component or circuit. For example, when two electrical conductors at different voltages are close together, the electric field between them causes electric charge to be stored on them; this effect is parasitic capacitance. Another example is a resistor designed to possess resistance, but that also has unwanted parasitic capacitance. The leads on a ceramic package substantially contribute to electrical parasitics. Widening the leads reduces the electrical parasitics. However, widening the leads require use of non-standard fabrication, assembly, test methods, and tooling. Widening the leads also causes lateral thermal stresses eventually resulting in lead buckling or failing lead attachments in the package. Another option to reduce electrical parasitics is to increase lead count or dimensions that negatively impact the foot print size of the package. Yet another option to reduce electrical parasitics is to use a fused portion at an entire length of the lead. Such a lead structure requires a broad land on the printed circuit board to which the leads are attached to and a broad braze pad on the package where accumulated stress leads to lead buckling or delamination.